1. Field of the Invention
This invention pertains to direct memory access ("DMA") of data and, more particularly, to processing both low and high priority DMA commands.
2. Description of the Related Art
Programmed computers typically execute a series of instructions that require the manipulation of data stored in the computer's memory. Execution of instructions is usually performed by one or more processors that can retrieve data from the computer's memory in several ways. One way is to simply retrieve the necessary data whenever the processor executes an instruction. Although this technique is commonly used in some situations, it is extremely inefficient when large amounts of data must be quickly processed. For instance, to execute a program on a floppy disk, the computer must transfer the program from the floppy disk to some predetermined location in the computer's memory. It would be extremely cumbersome and time consuming for a processor to execute a new command to retrieve every necessary piece of data to accomplish this transfer. Thus, processors commonly use another technique known as "direct memory access," or "DMA" for data retrieval in these situations.
DMA, in the most generic form, is the transfer of a block of data with a single instruction although there are many variations on the theme. The processor may execute the DMA instruction or it may command a special circuit known as a "DMA controller" to execute the instruction. For instance, the processor might command the DMA controller to transfer a block of data by programming the destination, the first memory location, and the block length. The DMA controller will then transfer a block of data having the length specified and beginning at the first memory location to the specified destination. The destination may be an input/output ("I/O") port or another location in memory.
DMA operations are typically performed by a DMA engine embedded in a DMA controller. DMA engines and their DMA techniques are well known in the art. Exemplary DMA engines known to the art include the DMA engine in the core of the Intel.RTM. 8237 DMA controller or that in the core of the Intel.RTM. 960 chipset. However, not all DMA engines are embedded in DMA controllers. DMA engines may be flexibly employed depended on the particular design criteria under which DMA is being implemented.
In today's demanding computing environment, DMA is widely used in complex applications. Processors generally, or at least occasionally, issue DMA commands to DMA controllers more quickly than the DMA controllers can process them. This high demand for DMA consequently is usually handled by placing DMA commands from a processor in a buffer. The DMA controller then retrieves the commands from the buffer and processes them in the order the processor issues them. Thus, because the first command received is the first command processed, the buffers are called "first in, first out," or "FIFO," buffers.
DMA operations in such environments are usually categorized as "low priority" or "high priority." Low priority and high priority DMA operations usually have separate buffers denominated the "low priority FIFO," or "LPF," and the "high priority FIFO," or "HPF." High priority DMA operations require expedited processing whereas low priority DMA operations do not. Thus, although DMA commands in an individual FIFO are processed in the order they are received, DMA commands are not always processed in the order the processor issues them. Furthermore, problems can arise when a long, low priority DMA operation is performed.
These problems are readily apparent in a program operating a graphical user interface such as Microsoft Corporation's Windows.RTM. program. If the computer delays processing the high priority DMA operation until the low priority operations finishes, the user may experience unacceptable interactive response of the graphical user interface. Alternatively, long, low priority DMA operations may be broken into a series of smaller, low priority DMA operations. High priority DMA operations can then be conducted between the smaller low priority operations. However, this alternative incurs increased overhead in the generation of low priority commands and requires much more complex FIFO management techniques that can slow the program's operating speed. Thus, there is a need for a new DMA management technique.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.